Jan-May 2022 |

This is a simulator model for the five stage pipeline processor built in c++.

• Developed a C++ simulation of a single-level Cache, offering Random, LRU, and Pseudo LRU replacement policies.
• Created a 5-stage Scalar Pipelined processor based on RISC Architecture, leveraging multithreading for parallel stage execution and improved overall performance.

You can also test the simulator with the testcases provided or create you own.